`include "CP0Defines.svh"
module EXE_MEM(
    input logic clk,
    input logic reset,
    input logic EXE_MEM_Flush,
    input logic EXE_MEM_Stall,

    input logic [31:0]EXE_PC,
    input logic [31:0]EXE_NPC,
    input logic [31:0]EXE_Instr,
    input logic [2:0]EXE_DMOp,
    input logic [31:0]EXE_Rt_Data,
    input logic EXE_DMWr,
    input logic [31:0]ALU_Out_End,
    input logic [4:0]EXE_RW,
    input logic EXE_MemToRegWr,
    input logic [1:0]EXE_Data_To_Reg_Sel,
    input logic EXE_IsBranch,
    input logic EXE_Immjump,
    input logic EXE_CP0Wr,
    input logic EXE_DMRd,
    input ExceptionType EXE_ExceptionTypeEnd,
    input logic [2:0]EXE_Reg_Writed_End,

    output logic [31:0]MEM_PC,
    output logic [31:0]MEM_NPC,
    output logic [31:0]MEM_Instr,
    output logic [2:0]MEM_DMOp,
    output logic [31:0]MEM_Data_Writed,
    output logic MEM_DMWr,
    output logic [31:0]MEM_ALU_Out,
    output logic [4:0]MEM_RW,
    output logic MEM_MemToRegWr,
    output logic [1:0]MEM_Data_To_Reg_Sel,
    output logic MEM_IsBranch,
    output logic MEM_Immjump,
    output logic MEM_CP0Wr,
    output logic MEM_DMRd,
    output ExceptionType MEM_ExceptionType,
    output logic [2:0]MEM_Reg_Writed
);
    always_ff @(posedge clk,negedge reset)begin
        if(!reset||EXE_MEM_Flush)begin
            MEM_PC <= 32'b0;
            MEM_NPC <= 32'b0;
            MEM_Instr <= 32'b0;
            MEM_DMOp <= 3'b0;
            MEM_Data_Writed <= 32'b0;
            MEM_DMWr <= 1'b0;
            MEM_ALU_Out <= 32'b0;
            MEM_RW <= 5'b0;
            MEM_MemToRegWr <= 1'b0;
            MEM_Data_To_Reg_Sel <= 2'b0;
            MEM_IsBranch<=1'b0;
            MEM_Immjump<=1'b0;
            MEM_CP0Wr<=1'b0;
            MEM_DMRd<=1'b0;
            MEM_ExceptionType<=`NoException;
            MEM_Reg_Writed <= 3'b0;
        end
        else if(!EXE_MEM_Stall)begin
            MEM_PC <= EXE_PC;
            MEM_NPC <= EXE_NPC;
            MEM_Instr <= EXE_Instr;
            MEM_DMOp <= EXE_DMOp;
            MEM_Data_Writed <= EXE_Rt_Data;
            MEM_DMWr <= EXE_DMWr;
            MEM_ALU_Out <= ALU_Out_End;
            MEM_RW <= EXE_RW;
            MEM_MemToRegWr <= EXE_MemToRegWr;
            MEM_Data_To_Reg_Sel <= EXE_Data_To_Reg_Sel;
            MEM_IsBranch<=EXE_IsBranch;
            MEM_Immjump<=EXE_Immjump;
            MEM_CP0Wr<=EXE_CP0Wr;
            MEM_DMRd<=EXE_DMRd;
            MEM_ExceptionType<=EXE_ExceptionTypeEnd;
            MEM_Reg_Writed <= EXE_Reg_Writed_End;
        end
        else 
            ;
    end
    
endmodule